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? semiconductor components industries, llc, 2013 march, 2013 ? rev. 0 1 publication order number: AND9131/d AND9131/d designing a led driver with the ncl30080/81/82/83 introduction as led lighting finds its way into low wattage applications, lamp designers are challenged for a variety of conflicting requirements. size is often dictated by the incumbent lamp and fixture size whether it?s a19, gu10, etc. thermal performance, reliability, safety, and emc requirements also present design challenges. the ncl3008x family of controllers incorporates all the features and protection needed to design compact low wattage led drivers with a minimum of external components. overview the ncl3008x is a family of 4 controllers in 2 different packages (micro 8 and tsop6). the 8 pin packaged parts have 2 extra pins for dimming and thermal / over voltage protection. the 6 pin package parts have all the basic control and protection feature required to make a low parts count led driver. table 1. product matrix product package thermal foldback analog/digital dimming 5 step log dimming ncl30080a/b tsop6 no no no ncl30081a/b tsop6 no no yes ncl30082a/b micro-8 yes yes no ncl30083a/b micro-8 yes soft-start yes in the a versions of the ncl3008x, some protections are latched. in the b versions, all faults are auto-recoverable. the controllers have a built in control algorithm that allows to precisely regulate the output current of a flyback converter from the primary side. this eliminates the need for an optocoupler and associated circuitry. th e control scheme also support buck-boost and sepic topology. the output current regulation is within 2% over a line range of 85-265 v rms. the power control uses a critical conduction mode (crm) approach with valley switching to optimize efficiency and emi filtering. the controller selects the appropriate valley for operation which keeps the frequency within a tighter range than would normally be possible with simple crm operation. constant current control in a flyback converter, the leakages inductances slow down the primary current decay and the secondary current rise. thus, the current transfer from primary to secondary side is delayed and the secondary peak current is reduced: i d,pk i l,pk n sp (eq. 1) the diode current reaches its peak when the leakage inductor is reset. thus, in order to accurately regulate the output current, the leakage inductor current must be taken into account. this is accomplished by sensing the clamping network current. practically, a node of the clamp capacitor is connected to r sense instead of the bulk voltage v bulk . then, by reading the voltage on the cs pin, we have an image of the primary current (red curve in figure 3). when the diode conducts, the secondary current decreases linearly from i d,pk to zero. when the diode current has turned off, the drain voltage begins to oscillate because of the resonating network formed by the inductors (l p +l leak ) and the lump capacitor. this voltage is reflected on the auxiliary winding wired in fly-back mode. thus, by looking at the auxiliary winding voltage, we can detect the end of the conduction time of secondary diode. the constant current control block picks up the leakage inductor current, the end of conduction of the output rectifier and controls the drain current to maintain the output current i out constant. we have: i out v ref 2n sp r sense (eq. 2) the output current value is set by choosing the sense resistor: r sense v ref 2n sp i out (eq. 3) http://onsemi.com application note
AND9131/d http://onsemi.com 2 from (eq.2), the first key point is that the output current is independent of the inductor value. moreover, the leakage inductance does not influence the output current value as the reset time is taken into account by the controller. figure 1. fly ? back currents and auxiliary winding voltage in dcm figure 2. flyback converter i l,pk i d,pk i pri (t) i sec (t) t 1 t 2 t demag v aux (t) v bulk v out r clamp c clamp r sense r cs c cs cs design rules for accurate current control in order to have an accurate regulation of the secondary current, the current-sense voltage shape must be the same as the primary current. figure 3 portrays the current sense waveform in green for an accurate output current regulation. figure 3. current sense voltage waveform for an accurate current regulation i l,pk i pri (t) t on t 1 i pri (t) the shape of the current-sense voltage will influence the output current regulation. indeed, the controller monitors when the current-sense voltage crosses the threshold for leakage inductance reset v cs(low) and calculate the output current set-point based on this information. thus, the shape of the cs voltage will influence the output current set-point. if the cs pin filter ( r lff , c cs ) is too big, the output current setpoint will vary ( i out higher than expected value). figure 5 shows the current-sense waveform in such case.
AND9131/d http://onsemi.com 3 figure 4. current ? sense pin figure 5. cs pin filter not optimized: cs shape differs from primary current shape i pri (t) r sense c cs r lff cs the zcd pin voltage is used to detect when the secondary current becomes null. it is important to filter the ringing caused by the leakage inductance and the lump capacitor if these oscillations have not decayed when the internal blanking timer t blank has elapsed. the demagnetization must be longer than t blank for accurate current regulation. if not, the controller will not be able to detect correctly the exact moment when the secondary current becomes null and the current regulation will greatly degrade. figure 6. optimal filtering of zcd pin voltage t blank t demag led driver specification in order to illustrate the design method that will be described in this document, we consider the following specification for a flyback led driver: table 2. led driver specification description symbol value units led driver specification minimum input voltage v in,min 85 v rms maximum input voltage v in,max 265 v rms minimum output voltage v out,min 12 v maximum output voltage v out,max 24 v output voltage at which the ovp is activated v out(ovp) 28 v output current (nominal) i out 0.5 a output rectifier voltage drop (estimated) v f 0.6 v input voltage for brown-in v in(start) 72 vrms startup time t startup 1.5 s
AND9131/d http://onsemi.com 4 table 2. led driver specification description units value symbol other parameters estimated efficiency 85 % estimated lump capacitor c lump 50 pf switching frequency at p out,max , v in,min f sw 45 khz estimated bulk voltage ripple v ripple 30 v sizing the components around the controller figure 7. generic application schematic r clamp d clamp c clamp r sense c vcc c bo r bol r lff c cs r ntc c sd c zcd r zcdl (optional) r zcd d ovp c bulk v dim r bou r start d out c out r dum m 1 the r zcd resistor limits the current flowing in the zcd pin. also, this resistor together with the c zcd capacitor delays the zero voltage crossing event and helps to tune the turn-on instant when the drain voltage is in the valley. to calculate r zcd , we must first determine the auxiliary winding voltage value during the on-time and the off-time. during the on-time, the voltage amplitude will reach its maximum value for the highest input voltage: v aux(low) n auxp v in,max 2 (eq. 4) during the off-time, we must consider the maximum output voltage value to calculate the auxiliary winding maximum voltage: v aux(high) n auxp n sp (v out v f ) (eq. 5) where: n auxp is the auxiliary to primary turn ratio: n auxp = n aux /n p then, the highest value of the aux winding voltage is used to calculate r zcd : r zcd max v aux(high) i zcd(max ) , v aux(low) i zcd(max ) (eq. 6) design example : the maximum input voltage is v in,max = 265 v rms. n auxp = 0.17. from the datasheet, we have: i zcd(max) = ? 2, + 5 ma v aux(high) n auxp n sp (v out,max v f ) 0.17 0.17 (28 0.5) 28.5 v (eq. 7) v aux(low) n auxp v in,max 2 0.17
265
2 (eq. 8) 63.7 v
AND9131/d http://onsemi.com 5 r zcd max v aux(high) i zcd(max ) , v aux(low) i zcd(max ) max 28.5 5m , 63.7 2m (eq. 9) max (5.7k, 31.8k) 31.8 k selecting the ntc there are different ways to select the thermistor depending on the critical parameter for the designer. we will consider the temperature t tfstart at which the thermal foldback starts and the temperature t otp at which the over temperature protection (otp) must triggers as our design parameters. the controller starts to reduce the output current when the voltage on sd pin drops below 1 v which correspond to a resistance between sd pin and ground: r sd 11.76 k . the current reduction is stopped when r sd 8 k : the output current is clamped to 50 % of its nominal value. the controllers detects an over temperature and shuts down when r sd 5.88 k . as a starting point, we can try to calculate the sensitivity index or constant b of the material needed to meet our temperature requirements. the formula for b can be found in the thermistor manufacturers? application notes or datasheets. to calculate the b value, it is necessary to know the resistances r 1 and r 2 of the thermistor at the temperatures t 1 and t 2 . b t 1 t 2 t 2 t 1 ln r 1 r 2 (eq. 10) in our case, this equation can be translated as follows: b x t otp t tfstart t otp t tfstart ln r tfstart r otp (eq. 11) where: t tfstart is the temperature at which the thermal foldback should start r tfstart is the corresponding resistance mentioned above: r tfstart = 11.76 k t otp is the temperature at which the otp must trigger r otp is the corresponding resistance mentioned above: r otp = 5.88 k generally, the b given by the manufacturer is calculated for 25 c and 85 c. the value of b depends on the temperatures by which it is calculated. that?s why in our case it is an approximate value and we might consider looking for a material within 5% of the calculated b x . then, we can use this b x value to approximate the resistance at 25 c of the thermistor needed: r 25 r tfstart e b x 1 t tfstart 1 25 273 (eq. 12) design example : t tfstart = 75 c = 348 k t otp = 95 c = 368 k b x t otp t tfstart t otp t tfstart ln r tfstart r otp 348
368 368 348 ln 11.76k 5.88k (eq. 13) 4438 k r 25 r tfstart e b x 1 t tfstart 1 25 273 11.76k e 4438 1 348 1 298 99.9 k (eq. 14) finally, we select a ntc with b 25/85 = 4220 and r 25 = 100 k . from the manufacturer tables of resistance vs temperature r(t) , we have the following values: r 75 = 13.16 k , r 80 = 11.06 k meaning the temperature foldback point is between 75 c and 80 c. r 95 = 6.74 k , r 100 = 5.76 k meaning the otp trip point is between 95 c and 100 c. it is also possible to place a resistor in parallel of the ntc to modify its r(t) characteristic. selecting the sd pin capacitor the sd pin capacitor must not exceed 4.7 nf so that the controller is able to start in every conditions, in particular when r sd is around 8 k . indeed at startup, the controller waits for 180 s minimum before starting the drv pulses in order to allow the current source to charge c sd . if a too big capacitor is used, the sd pin voltage will not be able to increase above 0.5 v before the 180 s timer ends. thus, the controller will detect an over temperature condition. designing the cs pin network (r lff , c cs ) the propagation delay t prop from the current-sense voltage reaching the programmed internal threshold v control to the mosfet off-state influences the output current regulation and must be taken into account. the peak current increase caused by t prop must be compensated. figure 8. propagation delay effect on peak current low line high line v control r sense i l,pkh i l,pkl t prop t prop i l time
AND9131/d http://onsemi.com 6 the propagation delay effect is compensated by applying an offset current proportional to the line voltage on the cs pin during the mosfet on-time only. the offset current is clamped when v pinvin > 5 v: i offset(max) = 76.5 a typical. the offset voltage amount is adjusted by connecting a resistor r lff between the cs pin and the sense resistor: v cs(offset) k lff v pinvin r lff (eq. 15) as a starting point, the offset resistor value can be estimated with: r lff 1 r bou r bol t pro p r sense l p k lff (eq. 16) where: k lff is the voltage to current conversion ratio on vin pin and can be found in the datasheets of the ncl30080/81/82/83. its typical value is 17 a / v. r bou and r bol are the brown-out resistors calculated in the next paragraph. the parameter t prop includes the propagation delay of the controller (50 ns typical from the datasheet) and of the mosfet gate drive. thus, it varies with the chosen mosfet and with the external elements added between the drv pin and the mosfet gate (series resistor, pnp transistor, ...). as a consequence, it is difficult to have an exact value for this parameter prior to the led driver design. as a first approximation, to calculate r lff , start with t prop = 150 ns. then, the offset resistor value can be adjusted by experiments to obtain a flat output current. using (eq.16), we can calculate the first value of r lff for our design: r lff 1 r bou r bol t pro p r sense l p k lff (eq. 17) 1 9.9meg 100k 150n
1.5 1900
17 696 after experiments in the lab, r lff value was increased to 820 . selecting the cs pin capacitor the shape of the current-sense voltage influences the output current regulation. if the cs pin filter ( r lff , c cs ) is too big, the output current setpoint will vary ( i out higher than expected value). thus, once r lff has been chosen, it is important to keep the value of c cs small to have a good regulation of the output current. c cs should be in the range of 10 ? 100 pf. selecting the brown-out resistors the controller starts switching when v cc > v cc(on) and when v pinvin > v bo(on) . figure 9. brown ? out circuit + ? bo_nok ? ? v bulk r bou vin c bo r bol controller starts switching if v pinvin > v bo(on) (1 v) controller stops switching if v pinvin < v bo(off) (0.9 v) after 50 ms fixed internal on / off thresholds: 50 ms blanking time first, select a value for r bol in the range of 10 k to 100 k . in order to decrease the power losses in the resistor network, it is better to choose a resistor in the range of 62 k to 100 k . for our design, we select r bol = 100 k . after that, select the input voltage at which the controller must start switching v in(start) . the upper brown-out resistor r bou value can be calculated with: r bou r bol v in(start) 2 v bo(on) 1 (eq. 18) the controller detects a brown-out condition and shuts down when the pin vin voltage stays below v bo(off) during 50 ms. thus, we can deduce the line voltage v in(stop) at which the controller stops switching: v in(stop) 1 2 r bou r bol r bol v bo(off) (eq. 19)
AND9131/d http://onsemi.com 7 design example : v in(start) = 71 v rms r bol = 100 k . r bou r bol v in(start) 2 v bo(on) 1 100k 71 2 1 1 (eq. 20) 9.94 m we choose r bou = 9.9 m . v in(stop) 1 2 r bou r bol r bol v bo(off) (eq. 21) 1 2 9.9m 100k 100k 0.9 63.6 vrms the controller stops when v in < 63.6 v rms. dimming pin (ncl30082 only) the ncl30082 dim pin has an enable threshold v dim(en) . in order to start pulsing, the dim pin voltage must be higher than v dim(en) . the dim pin combines analog and pwm dimming capability. if a signal lower than v dim100 is applied to this pin, the controller decreases the output current proportionally to the applied voltage. the following equation gives the relationship between the output current and the dim pin voltage: i out (%) 100 175 v dim 0.4 (eq. 22) for normal pwm dimming, apply a signal with a low state value below v dim(en) and high state value above v dim100 . it is also possible to apply a square signal with a high state value below v dim100 to further reduce the output current in pwm dimming (deep pwm dimming in figure 10). figure 10. analog / pwm dimming 0.7 v v dim v dim100 v dim(en) 100% i out 0% i out analog dimming pwm dimming deep pwm dimming
AND9131/d http://onsemi.com 8 startup network the ncl3008x consumes a low current during the startup (14 a typ., 30 a max.). thus, depending on the required startup time, high values of startup resistors can be used to reduce the power dissipation in the startup network. however, the device consumes a slightly higher current (60 a max.) during startup in fault mode, when the 4 ? s auto ? recovery timer is counting. the power supply designer must ensure that the startup current noted i startup on figure 11 is always above 60 a. the startup resistor r startup can either be connected to the bulk rail or to half-wave (figure 11). connecting the startup resistor to the half-wave allows decreasing the power dissipated in the startup resistor. figure 11. the startup resistor can be connected to the bulk rail or to the half wave i startup r startup c vcc c vcc l aux l aux i startup r startup / bulk rail connection half ? wave connection calculating the startup capacitor the startup capacitor is calculated to allow the power supply to close the loop before v cc falls below v cc(off) . thus, c vcc must be able to supply the controller alone until the auxiliary winding voltage v aux is high enough to supply the controller. the time duration where the controller is supplied by c vcc alone is noted t reg (figure 12). at startup, almost no current will flow through the led string until the output voltage exceeds the forward threshold of the led string. thus, we can consider that all the current charges the output capacitor. we can then roughly estimate the time t reg : t reg c out i out (v out1 v f ) n auxp n sp (eq. 23) where: v out1 is the corresponding output voltage at which the auxiliary winding should start to supply the controller figure 12. v cc waveform during startup t startup t reg
AND9131/d http://onsemi.com 9 the startup capacitor value can be calculated as follows: c vcc (i cc2 q g f sw )t reg v cc(on),min v cc(off),max (eq. 24) the current needed to charge c vcc alone during the startup is: i c vcc v cc(on),max c vcc t startup (eq. 25) design example : four our 10 w led driver, we chose a 3-a, 800-v mosfet (stp3nk80 from st microelectronics). the total gate charge is: q g = 19 nc the switching frequency at low line, maximum output load is: f sw = 55 khz. the total startup time of the led driver must be below 1.5 second at v in = 90 v rms. we choose: v out1 = 15 v from the datasheet, we can extract the values of the following parameters: i cc2 = 2.1 ma v cc(on),min = 16 v v cc(on),max = 20 v v cc(off),max = 9.4 v we can deduce: t reg c out i out (v out1 v f ) n auxp n sp (eq. 26) 120
10 6 0.470 (15 0.6) 0.17 0.17 4ms c vcc (i cc2 q g f sw )t reg v cc(on),min v cc(off),max (eq. 27) (2.1m 19n
55k)
4m 16 9.4 1.91 f we could choose a 2.2 f capacitor for c vcc but we must also consider the step dimming case of the ncl30083 where the output current is decreased by discrete steps each time a brown-out condition is detected. thus, we select a 4.7 f capacitor. the current needed to charge c vcc is: i c vcc v cc(on),max c vcc t startup 20
4.7 1.5 63 a (eq. 28) startup resistor calculation ? bulk connection if the resistor is connected to the bulk rail, the following formula can be used to calculate its value: r startup v in,min 2 i cvcc i cc(start) (eq. 29) where: i cvcc is the current needed to charge the vcc pin capacitor i cc(start) is the current consumed by the controller during startup v in,min is the minimum input voltage the maximum power dissipated by the startup resistor connected to the bulk rail is: p startup v in,max 2 v cc 2 r startup (eq. 30) ? half-wave connection if the resistor is connected to the half-wave: r startup1 2 v in,min 2 i cvcc i cc(start) r startup (eq. 31) the maximum power dissipated by the startup resistor connected to the half-wave is thus: p startup1 2 v in,max 2 v cc 2 r startup1 2 (eq. 32) design example : from the datasheet, the typical value of i cc(start) is 14 a. we deduce: r startup v in,min 2 i cvcc i cc(start),max 85 2 63 14 1.56 m (eq. 33) r startup1 2 v in,min 2 i cvcc i cc(start) 85 2 63 14 497 k (eq. 34) the power dissipated for each resistor at maximum input voltage is: p startup v in,max 2 v cc 2 r startup 265 2 20 2 1.56
10 6 81 mw (eq. 35) p startup1 2 v in,max 2 v cc 2 r startup1 2 265 2 20 2 497k 20 mw (eq. 36) connecting the startup resistor to the half-wave allows saving 60 mw! thus, we choose this approach for our led driver design.
AND9131/d http://onsemi.com 10 flyback transformer design the transformer is an important part of the power supply design as it will influence the choice of the mosfet, the output rectifier and the rcd clamp network. the transformer design is a compromise between performance and cost of the solution. for example, allowing higher drain-source voltage excursion will imply to use a mosfet with a larger breakdown voltage, but it will allow using an output rectifier with a smaller breakdown voltage. it will also decrease the power losses in the rcd clamp as we will be able to use higher clamping resistor value (provided that the leakage inductance of the transformer is kept under control). reflecting more output voltage will also decrease the maximum necessary primary peak current, but it will increase the secondary peak current. turn ratio calculation the constant current algorithm implemented in the ncl3008x provides a better regulation of the output current if the duty-cycle of the mosfet is equal or above 50%. the duty-cycle of a quasi-square wave resonant flyback converter operated in the 1 st valley can be calculated with: d v out v f n sp v in v out v f (eq. 37) the duty-cycle varies with the output load and the input voltage. in reality, we cannot have d > 0.5 for all input voltage / output loading conditions. thus, we will design the transformer in order to have a duty cycle greater than 50% at a chosen operating point, for example maximum output load and minimum input voltage. n sp v out,max v f 0.5 (v out,max v f ) v in,min 2 (eq. 38) for our led driver, we decide to have a duty-cycle around 55% at v out,max and v in,min : n sp v out,max v f 0.55 (v out,max v f ) v in,min 24 0.6 0.55 (24 0.6) 85 2 (eq. 39) n sp 0.167 maximum primary peak current and inductance the peak current is highest at minimum input voltage and maximum output load p out,max . by selecting a switching frequency for this operating point f sw,min , we can calculate the maximum peak current and the primary inductance value: i l,pk 2 p out,max 1 v in,min 2 v ripple n sp v out(ovp) v f (eq. 40) 2p out,max c lump f sw,min l p 2p out,max i l,pk 2 f sw,min (eq. 41) where: v ripple is the bulk voltage ripple c lump is the total capacitor at the drain node of the mofset. for a first approximation, we can use c oss value. v out(ovp) is the output voltage at which the over voltage protection must triggers is the estimated efficiency of the power supply using equations (40) and (41), we can calculate the maximum peak current and the primary inductance of the flyback transformer: i l,pk 2 p out,max 1 v in,min 2 v ripple n sp v out(ovp) v f (eq. 42) 2p out,max c lump f sw,min 2 28
0.5 0.85 1 85 2 30 0.167 28 0.6 2
28
0.5
50p
50k 0.85 i l,pk 0.59 a l p 2p out,max i l,pk 2 f sw,min 2
28
0.5 0.59 2
50k
0.84 (eq. 43) l p 1900 h
AND9131/d http://onsemi.com 11 choosing the mosfet breakdown voltage figure 13. mosfet drain ? source voltage at high line bv dss v ds,max v os v clamp v reflect v bulk,max 15% derating figure 13 shows the waveform of the drain-source voltage of a mosfet operated in the 1 st valley. we can estimate the maximum voltage reached on the drain node, considering v out(ovp) level as the maximum output voltage: v ds,max v in,max 2 (v out(ovp) v f ) n sp k c v os (eq. 44) where: k c is the clamping coefficient (k c = v clamp / v reflect ) [1]. k c should be keep in the range of 1.3 to 1.5 times the reflected voltage. v os is the drain voltage overshoot caused by the clamping diode recovery time. after calculating the maximum drain-source voltage, we apply a safety factor of 15% in order to select the breakdown voltage of the mosfet, meaning that: b vdss v ds,max (1 0.15) (eq. 45) the following table gives the maximum drain-source voltage considering a 15% derating factor for mosfet breakdown voltage found on the market. table 3. v ds,max after 15% derating has been applied to bv dss breakdown voltage (bv dss ) maximum drain-source voltage (v ds,max ) 500 v 425 v 600 v 510 v 650 v 553 v 800 v 680 v using (eq.44), we calculate the mosfet v ds,max in our design: v ds,max v in,max 2 (v out(ovp) v f ) n sp k c v os (eq. 46) 265 2 (28 0.6) 0.167 1.6 20 668 v looking at table 3, we select an 800 v mosfet. choosing the mosfet r dson space is very limited in a led bulb, and there is no space to add a heatsink for the power moset or the output rectifier. thus, the mosfet will be chosen such that it can dissipate the power in all conditions without using a heatsink. knowing the chosen package thermal resistance r ja , we first calculate the power that can be dissipated by this package at a chosen maximum ambient temperature t a(max) . p pack t j(max) t a(max) r ja (eq. 47) in a quasi-square wave resonant power supply operating at low line and full load, the mosfet losses are mainly conduction losse s. the mosfet r dson at t j(max) can be estimated: r dson t j p pack i pri,rms 2 (eq. 48) in equation (48), i pri,rms is the rms current in the primary side of the flyback transformer at lowest input voltage and full output load:
AND9131/d http://onsemi.com 12 i pri,rms i l,pk 1 3 i l,pk l p f sw,min v in,min 2 v ripple (eq. 49) we choose a to-220fp isolated package for the mosfet. from the manufacturer datasheet, we have: r ja = 62.5 c / w. we consider a maximum junction temperature of 125 c for this device. the maximum ambient temperature is 80 c. p pack t j(max) t a(max) r ja 125 80 62.5 0.72 w (eq. 50) the primary peak current and the primary inductance have been calculated in (42) and (43). we can deduce the primary rms current value: i pri,rms i l,pk 1 3 i l,pk l p f sw,min v in,min 2 v ripple (eq. 51) 0.62 1 3 0.59
1900
50k 82 2 30 0.268 a we deduce the r dson value at t j = 125 c: r dson(125 o c) p pack i pri,rms 2 0.72 0.268 2 10 (eq. 52) the mosfet manufacturers generally specify the r dson at 25 c. the r dson value at 25 c is roughly half the value at t j = 125 c, so we will choose a mosfet with a r dson(25 c) 5 . selecting the output diode in order to select the output diode, it is important to consider also the losses caused by the secondary rms current which interact with the diode dynamic resistance r d : p diode v f i out r d i sec,rms 2 (eq. 53) the diode dynamic resistance can be extracted from the i-v curves drawn in the datasheet of the diode or measured. figure 14. murs220 curves v f1 , i f1 v f2 , i f2 look at the forward voltage drop at i f1 = i out , then choose an operating point slightly below the previous one and note v f2 , i f2 . from these values, you can calculate the dynamic resistance: r d v f1 v f2 i f1 i f2 (eq. 54) we choose a murs220 diode in smb package. we extract its dynamic resistance from the curves in figure 14: r d = 167 m . the rms value of the current circulating in the secondary side of the transformer is: i sec,rms i l,pk n sp 1 3 1 i l,pk l p f sw,min v in,min 2 v ripple (eq. 55) 0.59 0.167 1 3 1 0.59
1900
50k 82 2 30 1.25 a
AND9131/d http://onsemi.com 13 the forward voltage drop of the murs220 diode at i out = 0.5 a and t j = 100 c is 0.65 v (figure 14). we can deduce the power dissipated by the diode: p diode v f i out r d i sec,rms 2 (eq. 56) 0.65
0.5 0.167
1.25 2 0.59 w when selecting the output diode, the power supply designer must ensure that the diode package is able to dissipate the calculated power: p pack > p diode . considering a thermal resistance r ja = 100 c/w for the smb package and a maximum junction temperature of 150 c for the diode, we calculate the power dissipation of the package using (eq.47): p pack t j(max) t a(max) r ja 150 80 100 0.7 w (eq. 57) since the worst case power losses in the output diode is 0.59 w and the package can dissipate 0.7 w at an ambient temperature of 80 c, we can consider our design safe. conclusion this application note provides the key equations and design criteria to dimension a primary-side constant current flyback converter operated by the ncl30080/81/82/83. the design method is illustrated by an implementation of a 12 w, wide mains led driver. table 4 summarizes the equations useful to select the components around the ncl3008x controllers. for detailed information on the performance of the 10 w led driver designed in this document, you can refer to and9132/d [2]. table 4. general equations summary zcd pin zcd pin resistor r zcd max v aux(high) 5m , v aux(low) 2m sd pin ntc b x coefficient and resistance at 25 c b x t otp t tfstart t otp t tfstart ln 11.76k 5.88k r 25 11.76k e b x 1 t tfstart 1 25 273 sd pin capacitor c sd 4.7 nf cs pin lff resistor r lff 1 r bou r bol t pro p r sense l p 17 cs pin capacitor 10 ? 100 pf vin pin lower resistor 10 ? 100 k upper resistor r bou r bol v in(start) 2 v bo(on) 1 dim pin output current variation with dim pin voltage i out (%) 100 175 v dim 0.4 startup network v cc capacitor c vcc (i cc2 q g f sw )t reg v cc(on),min v cc(off),max startup resistor (bulk connection) r startup v in,min 2 i cvcc 14 (half-wave connection) r startup startup current i start 60 a! sense resistor set the output current value r sense 0.25 2n sp i out
AND9131/d http://onsemi.com 14 table 4. general equations summary transformer design turn-ratio n sp v out,max v f 0.5 (v out,max v f ) v in,min 2 maximum primary peak current i l,pk 2 p out,max 1 v in,min 2 v ripple n sp v out(ovp) v f 2p out,max c lump f sw,min primary inductance l p 2p out,max i l,pk 2 f sw,min mosfet selection breakdown voltage b vdss v ds,max (1 0.15) v ds,max v in,max 2 (v out(ovp) v f ) n sp k c v os r ds(on) at t j = 125 c i pri,rms i l,pk 1 3 i l,pk l p f sw,min v in,min 2 v ripple p pack 125 t a(max) r ja r dson(125 o c) p pack i pri,rms 2 output diode diode losses p diode v f i out r d i sec,rms 2 i sec,rms i l,pk n sp 1 3 1 i l,pk l p f sw,min v in,min 2 v ripple references [1] christophe basso, ?switch-mode power supplies?, mcgraw-hill, 2008. [2] stphanie cannenterre, ?performance of a 10 w led driver controlled by the ncl30080-81-82-83?, and9132/d on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 AND9131/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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